| 2017 | DATE | Tunnel FET based refresh-free-DRAM. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | DATE | 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | ISCAS | Ultra-compact SRAM design using TFETs for low power low voltage applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2015 | ISCAS | Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. | Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel |
| 2013 | ISCAS | CMOS SRAM scaling limits under optimum stability constraints. | Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu |
| 2012 | DATE | Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. | Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara |
| 2012 | ISCAS | A 32nm tunnel FET SRAM for ultra low leakage. | Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2009 | ISCAS | SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. | Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara |