| 2023 | ACSSC | Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re |
| 2020 | ACSSC | FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Span |
| 2020 | ARITH | Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors. | Alberto Nannarelli |
| 2019 | ACSSC | Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re |
| 2018 | ACSSC | A Power Efficient Digital Front-End for Cognitive Radio Systems. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re |
| 2018 | ARITH | Tunable Floating-Point for Energy Efficient Accelerators. | Alberto Nannarelli |
| 2016 | ACSSC | Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. | A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re |
| 2013 | ACSSC | Truncated multipliers through power-gating for degrading precision arithmetic. | Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re |
| 2012 | ACSSC | Imprecise arithmetic for low power image processing. | Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re |
| 2012 | ACSSC | Power efficient design of parallel/serial FIR filters in RNS. | Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re |
| 2011 | ARITH | Radix-16 Combined Division and Square Root Unit. | Alberto Nannarelli |
| 2010 | DATE | Post-placement temperature reduction techniques. | Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2008 | ACSSC | Power dissipation in division. | Wei Liu, Alberto Nannarelli |
| 2008 | ACSSC | Reducing power dissipation in pipelined accumulators. | Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re |
| 2008 | ACSSC | Session TP8b1: Computer arithmetic II. | Alberto Nannarelli |
| 2008 | ISCAS | ADAPTO: full-adder based reconfigurable architecture for bit level operations. | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli |
| 2008 | ISCAS | A variant of a radix-10 combinational multiplier. | Luigi Dadda, Alberto Nannarelli |
| 2007 | ISCAS | Low-power adaptive filter based on RNS components. | G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2005 | ARITH | Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. | Elisardo Antelo, Toms Lang, Paolo Montuschi, Alberto Nannarelli |
| 2005 | ISCAS | Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2004 | DATE | A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. | Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2004 | ISCAS | Low-power implementation of polyphase filters in Quadratic Residue Number system. | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2003 | ISCAS | Power-delay tradeoffs in residue number system. | Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re |
| 2002 | ISCAS | Power characterization of digital filters implemented on FPGA. | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2001 | ISCAS | Tradeoffs between residue number system and traditional FIR filters. | Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli |
| 2001 | ISCAS | FPGA realization of RNS to binary signed conversion architecture. | Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono |
| 2001 | ISLPED | Cached-code compression for energy minimization in embedded processors. | Luca Benini, Alberto Macii, Alberto Nannarelli |
| 1999 | ARITH | Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. | Alberto Nannarelli, Toms Lang |
| 1999 | ICCD | Low-Power Radix-4 Combined Division and Square Root. | Alberto Nannarelli, Toms Lang |
| 1998 | ICCD | Low-power radix-8 divider. | Alberto Nannarelli, Toms Lang |
| 1998 | ISLPED | Power-delay tradeoffs for radix-4 and radix-8 dividers. | Alberto Nannarelli, Toms Lang |
| 1996 | ISLPED | Low-power radix-4 divider. | Alberto Nannarelli, Toms Lang |