| 2026 | ISCAS | A Fully-Parallel Digital MRAM Computing-in-Memory Macro Featuring a High-Efficient Dynamic Adder Tree and Bit-Splitting MAC. | Zhongzhen Tong, Jiye Yao, Shaohui Ma, Yulong Qiu, Zhaohao Wang, Amara Amara, Xiaoyang Lin |
| 2025 | ISCAS | ASP: A daptive Sparse LUT-based Bit-Slice Accelerator for Efficient CNN Inference. | Yueting Li, Yulong Qiu, Amara Amara |
| 2021 | ISCAS | Unobtrusive Smart Mat System for Sleep Posture Recognition. | Haikang Diao, Chen Chen, Wei Chen, Wei Yuan, Amara Amara |
| 2019 | ICTD | ICTs as catalysts in child protection programmes: current landscape in South Asia & a concept to inform future use. | Balwant Godara, Nihaalini Kumar, Frederique Boursin, Gatienne Jobit, Amara Amara, Thierry Agagliate |
| 2017 | DATE | Tunnel FET based refresh-free-DRAM. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | DATE | 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | ISCAS | Ultra-compact SRAM design using TFETs for low power low voltage applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | ISCAS | A cost-effective approach for ubiquitous broadband access based on hybrid PLC-VLC system. | Jian Song, Sicong Liu, Guangxin Zhou, Bingyan Yu, Wenbo Ding, Fang Yang, Hongming Zhang, Xun Zhang, Amara Amara |
| 2015 | ISCAS | Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. | Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel |
| 2015 | ISCAS | 0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell. | Kiyoo Itoh, Khaja Ahmad Shaik, Amara Amara |
| 2013 | ISCAS | CMOS SRAM scaling limits under optimum stability constraints. | Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu |
| 2012 | DATE | Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. | Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara |
| 2012 | ISCAS | A 32nm tunnel FET SRAM for ultra low leakage. | Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2010 | ISCAS | 32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. | Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Branger, Marie-Anne Jaud, J. Dura, P. Perreau, Frdric Boeuf, Franois Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Andrei Vladimirescu, Amara Amara |
| 2009 | ISCAS | SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. | Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara |
| 2008 | ISCAS | A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. | Bastien Giraud, Amara Amara |
| 2007 | ISCAS | A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. | Bastien Giraud, Amara Amara, Andrei Vladimirescu |
| 2005 | ICIP | Iris identification and robustness evaluation of a wavelet packets based algorithm. | Florence Rossant, Frdric Amiel, Thomas Ea, Amara Amara, Manuel Torres Eslava |
| 2005 | ISCAS | Ultra low voltage design considerations of SOI SRAM memory cells. | Olivier Thomas, Amara Amara |
| 2004 | ICIP | IRIS features extraction using wavelet packets. | Erik Rydgren, Thomas Ea, Frdric Amiel, Florence Rossant, Amara Amara |
| 2003 | ISCAS | An SOI 4 transistors self-refresh ultra-low-voltage memory cell. | Olivier Thomas, Amara Amara |
| 2001 | ISCAS | Static power consumption management in CMOS memories. | Arnaud Turier, Lotfi Ben Ammar, Amara Amara |