| 2020 | ISCAS | Gain-Cell Embedded DRAMs: Modeling and Design Space. | Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg |
| 2020 | ISCAS | GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. | Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman |
| 2019 | DAC | FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems. | Marco Widmer, Andrea Bonetti, Andreas Burg |
| 2019 | ISCAS | Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space. | Ester Vicario Bravo, Andrea Bonetti, Andreas Burg |
| 2018 | ISCAS | A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. | Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg |
| 2015 | DATE | A tool for the assisted design of charge redistribution SAR ADCs. | Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita |
| 2015 | ISCAS | An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. | Andrea Bonetti, Adam Teman, Andreas Burg |
| 2015 | ISCAS | Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. | Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg |