Andrei Vladimirescu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
16
Venues
3
Active years
1987–2026
Best venue rank
A*
Where they publish
Papers
16 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Simulator-Driven Deep Reinforcement Learning for Analog Circuit Design. | Felicia B. Guo, Ken T. Ho, Andrei Vladimirescu, Borivoje Nikolic |
| 2019 | ISCAS | Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers. | Mohammadreza Mehrpoo, Bishnu Patra, Jiang Gong, Pascal Alexander 't Hart, Jeroen P. G. van Dijk, Harald Homulle, Gerd Kiene, Andrei Vladimirescu, Fabio Sebastiano, Edoardo Charbon, Masoud Babaie |
| 2018 | DATE | A co-design methodology for scalable quantum processors and their classical electronic interface. | Jeroen P. G. van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano |
| 2017 | DAC | Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited. | Fabio Sebastiano, Harald Homulle, Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Lin Song, Masoud Babaie, Andrei Vladimirescu, Edoardo Charbon |
| 2017 | DATE | Tunnel FET based refresh-free-DRAM. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | DATE | 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | ISCAS | Ultra-compact SRAM design using TFETs for low power low voltage applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2015 | ISCAS | Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. | Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel |
| 2013 | ISCAS | CMOS SRAM scaling limits under optimum stability constraints. | Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu |
| 2012 | DATE | Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. | Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara |
| 2012 | ISCAS | A 32nm tunnel FET SRAM for ultra low leakage. | Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2010 | ISCAS | 32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. | Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Branger, Marie-Anne Jaud, J. Dura, P. Perreau, Frdric Boeuf, Franois Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Andrei Vladimirescu, Amara Amara |
| 2009 | ISCAS | SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. | Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara |
| 2007 | ISCAS | A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. | Bastien Giraud, Amara Amara, Andrei Vladimirescu |
| 2006 | ISCAS | Analog circuit synthesis using standard EDA tools. | Andrei Vladimirescu, Radu Zlatanovici, Paul G. A. Jespers |
| 1987 | DAC | A Vector Hardware Accelerator with Circuit Simulation Emphasis. | Andrei Vladimirescu, David Weiss, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass |