| 2018 | CCS | HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security. | Andrew Ferraiuolo, Mark Zhao, Andrew C. Myers, G. Edward Suh |
| 2018 | CCS | Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control. | Jed Liu, Joe Corbett-Davies, Andrew Ferraiuolo, Alexander Ivanov, Mulong Luo, G. Edward Suh, Andrew C. Myers, Mark E. Campbell |
| 2017 | ASPLOS | Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis. | Andrew Ferraiuolo, Rui Xu, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
| 2017 | DAC | Secure Information Flow Verification with Mutable Dependent Types. | Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh |
| 2017 | SOSP | Komodo: Using verification to disentangle secure-enclave hardware from software. | Andrew Ferraiuolo, Andrew Baumann, Chris Hawblitzel, Bryan Parno |
| 2016 | DAC | SecDCP: secure dynamic cache partitioning for efficient timing channel protection. | Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
| 2016 | HPCA | Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller. | Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
| 2014 | HPCA | Low-overhead and high coverage run-time race detection through selective meta-data management. | Ruirui C. Huang, Erik Halberg, Andrew Ferraiuolo, G. Edward Suh |
| 2014 | HPCA | Timing channel protection for a shared memory controller. | Yao Wang, Andrew Ferraiuolo, G. Edward Suh |
| 2012 | ICCAD | Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC. | Andrew Ferraiuolo, Xuehui Zhang, Mohammad Tehranipoor |