| 2025 | DAC | Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories. | Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu |
| 2025 | ISCAS | Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems. | Yuyao Kong, Jianwei Jia, Anni Lu, Faaiq G. Waqar, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu |
| 2024 | ASPDAC | A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. | Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu |
| 2024 | DAC | Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. | Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu |
| 2023 | IJCNN | CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators. | Minah Lee, Anni Lu, Mandovi Mukherjee, Shimeng Yu, Saibal Mukhopadhyay |
| 2021 | DATE | A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. | Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu |