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Atsushi Kamo

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

7

Venues

2

Active years

1999–2005

Best venue rank

C

Where they publish

Papers

7 indexed papers, newest first.

YearVenueTitleAuthors
2005ISCASModified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits.Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2004DATEHybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits.Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2002ISCASOptimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method.I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2002ISCASNoise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique.Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2001ISCASHigh-speed interconnect simulation using MIMO type of adaptive least square method.Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
2001ISCASSimulation for the optimal placement of decoupling capacitors on printed circuit board.Atsushi Kamo, Takayuki Watanabe, Hideki Asai
1999ISCASExpanded GMC for transient analysis of transmission line networks.Atsushi Kamo, Takayuki Watanabe, Hideki Asai