| 2024 | QCE | Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits. | David Clarino, Kyouhei Seino, Atsushi Matsuo, Shigeru Yamashita |
| 2024 | QCE | Optimization for Gaussian Elimination-Based NNA-Compliant Circuit Synthesis Method by Inserting CN OT Gates. | Zanhe Qi, Atsushi Matsuo, Shigeru Yamashita |
| 2021 | ASPDAC | Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures. | Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita |
| 2021 | RC | Variational Quantum Eigensolver and Its Applications. | Atsushi Matsuo |
| 2019 | ASPDAC | Quantum circuit compilers using gate commutation rules. | Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross |
| 2019 | ISCAS | Reducing the Overhead of Mapping Quantum Circuits to IBM Q System. | Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita |
| 2019 | RC | An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid. | Atsushi Matsuo, Shigeru Yamashita |
| 2011 | RC | Changing the Gate Order for Optimal LNN Conversion. | Atsushi Matsuo, Shigeru Yamashita |
| 2004 | ER | An Ontological Framework for Evolutionary Model Management. | Atsushi Matsuo, Kazuhisa Seta, Yusuke Hayashi, Mitsuru Ikeda |