| 2026 | ASPDAC | BIHDC: A Retrainable Fully-Binary Hyperdimensional Computing Accelerator for Edge FPGAs. | Changzhen Han, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu |
| 2026 | ISCAS | An 8T-SRAM Near-Memory Architecture for Multiplierless Approximate DCT. | Xu Wang, Ke Chen, Bi Wu, Chenggang Yan, Lixia Han, Chenghua Wang, Weiqiang Liu |
| 2026 | ISCAS | A Low Complexity BPF Polar Decoder Design with Sensitivity-Aware LUT Compression Framework. | Bozhi Xiu, Yanjing Zhang, Chenggang Yan, Ke Chen, Bi Wu, Weiqiang Liu |
| 2025 | DAC | PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing. | Ziying Cui, Ke Chen, Bi Wu, Yu Gong, Chenggang Yan, Weiqiang Liu |
| 2025 | DAC | MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach. | Xuehui Liu, Xueyan Wang, Tianyang Yu, Chen Cheng, Shuo Ran, Bi Wu, Xiaotao Jia, Weiqiang Liu, Gang Qu, Weisheng Zhao |
| 2025 | ISCAS | High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme. | Kai Tian, Bi Wu, Ke Chen, Weiqiang Liu |
| 2025 | ISCAS | Learning-Based Realtime Synthetic Aperture Radar Imaging for Embedded System on Satellite. | Tianyang Yu, Bi Wu, Weiqiang Liu |
| 2024 | ARITH | A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration. | Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Yu Gong, Weiqiang Liu |
| 2024 | DAC | A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration. | Xidi Ma, Weichen Zhang, Xueyan Wang, Tianyang Yu, Bi Wu, Gang Qu, Weisheng Zhao |
| 2024 | ISCAS | Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models. | Bin Gong, Ke Chen, Pengfei Huang, Bi Wu, Weiqiang Liu |
| 2022 | ICCD | Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration. | Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu |
| 2018 | IJCNN | Optical Flow Based Face Hallucination Via Weightedly-Constrained Representation. | Bi Wu, Zhihua Cai, Xiaobo Liu |
| 2017 | ICCAD | Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. | Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao |
| 2016 | DAC | PDS: pseudo-differential sensing scheme for STT-MRAM. | Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao |
| 2012 | VEE | Block storage virtualization with commodity secure digital cards. | Harvey Tuch, Cyprien Laplace, Kenneth C. Barr, Bi Wu |
| 2011 | COMSNETS | CrowdLab: An architecture for volunteer mobile testbeds. | Eduardo Cuervo, Peter Gilbert, Bi Wu, Landon P. Cox |