| 2013 | ISCAS | A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique. | I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, Soon-Jyh Chang |
| 2012 | ICCAD | Performance-driven analog placement considering monotonic current paths. | Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu |
| 2010 | ISCAS | Low complexity MAD prediction algorithms for rate controllable H.264/AVC hardware encoders. | Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu |
| 2009 | ICIP | Lossless image and video coding based on H.264/AVC intra predictions with simplified interpolations. | Shih-Tse Wei, Shang-Ru Shen, Bin-Da Liu, Jar-Ferr Yang |
| 2009 | ISCAS | Design of One-cycle Control Power Factor Correction IC with Unipolar Supply Voltage. | Kai-Chi Chang, Kai-Hui Chen, Tsorng-Juu Liang, Bin-Da Liu |
| 2009 | ISCAS | Transform-domain Partial Prediction Algorithm for Intra Prediction in H.264/AVC. | Chia-Wei Tien, Heng-Yao Lin, Bin-Da Liu, Jar-Ferr Yang |
| 2009 | ISCAS | Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories. | Jianwei Zhang, Yizheng Ye, Bin-Da Liu, Feng Guan |
| 2008 | ISCAS | System level design of a spatio-temporal video resampling architecture. | Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu, Bin-Da Liu |
| 2007 | ISCAS | A Real Time and Low Cost Hardware Architecture for Video Abstraction System. | Li-Chuan Chang, Yen-Sung Chen, Rung-Wen Liou, Chih-Hung Kuo, Chia-Hung Yeh, Bin-Da Liu |
| 2007 | ISCAS | Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu |
| 2006 | ISCAS | Low power design of H.264 CAVLC decoder. | Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang |
| 2006 | ISCAS | Efficient deblocking filter architecture for H.264 video coders. | Heng-Yao Lin, Jwu-Jin Yang, Bin-Da Liu, Jar-Ferr Yang |
| 2006 | ISLPED | A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. | Jianwei Zhang, Yizheng Ye, Bin-Da Liu |
| 2005 | ISCAS | Combined 2-D transform and quantization architectures for H.264 video coders. | Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
| 2005 | ISCAS | A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. | Hsin-Hung Ou, Bin-Da Liu |
| 2004 | ISCAS | Unified selectable fixed-coefficient recursive structures for computing DCT, IMDCT and subband synthesis filtering. | Zhan-Yuan Cheng, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
| 2004 | ISCAS | Condensed recursive structures for computing multi-dimensional DCT with arbitrary length. | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
| 2004 | ISLPED | A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. | Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu |
| 2003 | ISCAS | Direct recursive structures for computing radix-r two-dimensional DCT. | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
| 2003 | ISCAS | Low-power and low-voltage fully parallel content-addressable memory. | Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu |
| 2002 | ISCAS | Design of a pipelined and expandable sorting architecture with simple control scheme. | Chi-Sheng Lin, Bin-Da Liu |
| 2002 | ISCAS | A scalable sorting architecture based on maskable WTA/MAX circuit. | Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu |
| 2001 | ISCAS | A hardware design approach for merge-sorting network. | Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu |
| 2001 | ISCAS | Adaptive postprocessors with DCT-based block classifications. | Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang |
| 2001 | ISCAS | A new level converter for low-power applications. | Chien-Cheng Yu, Weiping Wang, Bin-Da Liu |
| 1996 | ICIP | Design of a color reproduction neural network chip with on-chip learning capability. | Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu |
| 1995 | DATE | Built-in intermediate voltage testing for CMOS circuits. | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu |
| 1995 | ISCAS | An I | Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee |
| 1994 | ISCAS | Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS Circuits. | Bin-Da Liu, Chun-Yueh Huang |
| 1993 | ICCAD | A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang |
| 1993 | ISCAS | Functional Text Pattern Generation for Asynchronous Circuits. | Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu |
| 1993 | ISCAS | Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang |
| 1992 | ICCAD | Overall consideration of scan design and test generation. | Pao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang |