| 2002 | ISCAS | An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. | Alex Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim |
| 2001 | DAC | Panel: Is Nanometer Design Under Control? | Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang |
| 2000 | IJCNN | Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses. | Alex Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu |
| 1997 | ICCD | A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. | Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu |
| 1996 | ICCD | A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. | David C. Chen, Bing J. Sheu, Theodore W. Berger |
| 1995 | ICCD | VLSI design of densely-connected array processors. | Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang |
| 1995 | ICCD | Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. | Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau |
| 1995 | ISCAS | Constructing Intelligent Microsystems with Modular VLSI Networks Design. | Bing J. Sheu |
| 1995 | ISCAS | VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. | Bing J. Sheu, Sa Hyun Bang, Wai-Chi Fang |
| 1995 | ISCAS | VLSI Neural Network Implementation of a Hippocampal Model. | Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai |
| 1995 | ISCAS | VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. | Bing J. Sheu, Robert C. Chang, Tony H. Wu, Sa Hyun Bang |
| 1994 | ISCAS | Search of Optimal Solutions in Multi-Level Neural Networks. | Sa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang |
| 1994 | ISCAS | An Analog MOS Model for Circuit Simulation and Benchmark Test Results. | Robert Chen-Hao Chang, Bing J. Sheu |
| 1994 | ISCAS | A Gaussian Synapse Circuit for Analog VLSI Neural Networks. | Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang |
| 1992 | DCC | An Adaptive High-Speed Lossy Data Compression. | Oscal T.-C. Chen, Zhen Zhang, Bing J. Sheu |
| 1992 | ICASSP | Design of a multiprocessor DSP chip for flexible information processing. | Chia-Fen Chang, Bing J. Sheu, Hiroto Okada |
| 1992 | ICASSP | Adaptive vector quantizer for image compression using self-organization approach. | Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang |
| 1991 | DCC | A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression. | Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen |
| 1991 | ICASSP | A VLSI neuroprocessor for real-time image flow computing. | Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee |
| 1991 | ICASSP | Real-time high-ratio image compression using adaptive VLSI neuroprocessors. | Bing J. Sheu, Wai-Chi Fang |
| 1991 | ICCD | A GaAs Receiver Module for Optoelectronic Computing and Interconnection. | Joongho Choi, Bing J. Sheu |
| 1991 | ICCD | Testing of Analog Neural Array-Processor Chips. | Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda |
| 1990 | ICCD | Automatic layout generation for mixed analog-digital VLSI neural chips. | David J. Chen, Bing J. Sheu |
| 1990 | ICCD | Real-time computing of optical flow using adaptive VLSI neuroprocessors. | Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee |
| 1990 | ICCD | Parallel digital image restoration using adaptive VLSI neural chips. | Ji-Chien Lee, Bing J. Sheu |
| 1990 | IJCNN | VLSI image processor using analog programmable synapses and neurons. | Bang W. Lee, Ji-Chien Lee, Bing J. Sheu |
| 1989 | ICCD | SLAM: a smart analog module layout generator for mixed analog-digital VLSI design. | David J. Chen, Ji-Chien Lee, Bing J. Sheu |
| 1989 | ICCD | Digital and analog integrated-circuit design with built-in reliability. | Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree |
| 1988 | ICCD | Knowledge-based analog circuit synthesis with flexible architecture. | Antony H. Fung, David J. Chen, Ying-Nan Lai, Bing J. Sheu |