| 2023 | ISCAS | A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing. | Zhengzhe Wei, Junjie Mu, Zhongzhiguang Lu, Yuanjin Zheng, Tony Tae-Hyoung Kim, Bongjin Kim |
| 2023 | ISCAS | 282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. | Qibang Zang, Wang Ling Goh, Lu Lu, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do |
| 2020 | DATE | A 16128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length. | Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim |
| 2020 | ISCAS | A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. | Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon |
| 2020 | ISCAS | Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing. | Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim |
| 2020 | ISCAS | A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks. | Junjie Mu, Bongjin Kim |
| 2019 | ISLPED | A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. | Taegeun Yoo, Hyunjoon Kim, Qian Chen, Tony Tae-Hyoung Kim, Bongjin Kim |
| 2013 | VTC | Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. | Injae Yoo, Bongjin Kim, In-Cheol Park |
| 2012 | ICCAD | Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. | Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar |
| 2011 | ISCAS | QC-LDPC Decoding Architecture based on Stride Scheduling. | Bongjin Kim, In-Cheol Park |
| 2010 | ISCAS | Dual-rail decoding of low-density parity-check codes. | Bongjin Kim, Hasan Ahmed, In-Cheol Park |