Bruno Dutertre
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
27
Venues
16
Active years
1995–2026
Best venue rank
A*
Where they publish
Papers
27 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | IJCAR | Checking Regular Expressions in Cvc5 Proofs. | Ofec Israel, Yoni Zohar, Andrew Reynolds, S. Hitarth, Bruno Dutertre, Clark W. Barrett, Cesare Tinelli |
| 2024 | FMCAD | SMT-D: New Strategies for Portfolio-Based SMT Solving. | Clark W. Barrett, Pei-Wei Chen, Byron Cook, Bruno Dutertre, Robert B. Jones, Nham Le, Andrew Reynolds, Kunal Sheth, Christopher Stephens, Michael W. Whalen |
| 2024 | FMCAD | Extending DRAT to SMT. | S. Hitarth, Cayden R. Codel, Hanna Lachnitt, Bruno Dutertre |
| 2024 | FMCAD | Solving String Constraints with Concatenation Using SAT. | Kevin Lotz, Amit Goel, Bruno Dutertre, Benjamin Kiesl-Reiter, Soonho Kong, Dirk Nowotka |
| 2024 | SAT | Quantum Circuit Mapping Based on Incremental and Parallel SAT Solving. | Jiong Yang, Yaroslav A. Kharkov, Yunong Shi, Marijn J. H. Heule, Bruno Dutertre |
| 2023 | CAV | Solving String Constraints Using SAT. | Kevin Lotz, Amit Goel, Bruno Dutertre, Benjamin Kiesl-Reiter, Soonho Kong, Rupak Majumdar, Dirk Nowotka |
| 2021 | CAV | Interpolation and Model Checking for Nonlinear Arithmetic. | Dejan Jovanovic, Bruno Dutertre |
| 2020 | CADE | Solving Bitvectors with MCSAT: Explanations from Bits and Pieces. | Stphane Graham-Lengrand, Dejan Jovanovic, Bruno Dutertre |
| 2016 | FMCAD | Property-directed k-induction. | Dejan Jovanovic, Bruno Dutertre |
| 2015 | CADE | Program Synthesis Using Dual Interpretation. | Ashish Tiwari, Adri Gascn, Bruno Dutertre |
| 2014 | CAV | Yices 2.2. | Bruno Dutertre |
| 2014 | FMCAD | Template-based circuit understanding. | Adri Gascn, Pramod Subramanyan, Bruno Dutertre, Ashish Tiwari, Dejan Jovanovic, Sharad Malik |
| 2013 | FMCAD | Simplex with sum of infeasibilities for SMT. | Tim King, Clark W. Barrett, Bruno Dutertre |
| 2011 | PRDC | Layered Diagnosis and Clock-Rate Correction for the TTEthernet Clock Synchronization Protocol. | Wilfried Steiner, Bruno Dutertre |
| 2010 | FMICS | SMT-Based Formal Verification of a | Wilfried Steiner, Bruno Dutertre |
| 2008 | ISORC | Modeling and Verification of Time-Triggered Communication Protocols. | Maria Sorea, Bruno Dutertre, Wilfried Steiner |
| 2007 | CAV | A Tutorial on Satisfiability Modulo Theories. | Leonardo Mendona de Moura, Bruno Dutertre, Natarajan Shankar |
| 2006 | CAV | A Fast Linear-Arithmetic Solver for DPLL(T). | Bruno Dutertre, Leonardo Mendona de Moura |
| 2004 | ICSE | Feature-Based Decomposition of Inductive Proofs Applied to Real-Time Avionics Software: An Experience Report. | Vu Ha, Murali Rangarajan, Darren D. Cofer, Harald Rue, Bruno Dutertre |
| 2003 | ACSAC | Forum Session: Security for Wireless Sensor Networks. | David Carman, Daniel Coffin, Bruno Dutertre, Vipin Swarup, Ronald J. Watro |
| 2003 | CCS | Self-regenerative software components. | Hassen Sadi, Bruno Dutertre, Joshua Levy, Alfonso Valdes |
| 2002 | SP | Intrusion-Tolerant Enclaves. | Bruno Dutertre, Valentin Crettaz, Victoria Stavridou |
| 2002 | RTSS | Dynamic Scan Scheduling. | Bruno Dutertre |
| 2001 | DSN | Intrusion-Tolerant Group Management in Enclaves. | Bruno Dutertre, Hassen Sadi, Victoria Stavridou |
| 2000 | RTSS | Formal Analysis of the Priority Ceiling Protocol. | Bruno Dutertre |
| 1999 | FM | A Formalization of Software Architecture. | John Herbert, Bruno Dutertre, Robert A. Riemenschneider, Victoria Stavridou |
| 1995 | LICS | Complete Proof Systems for First Order Interval Temporal Logic | Bruno Dutertre |