Byong-Tae Chung
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2010–2010
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | ISCAS | A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. | Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih |
| 2010 | ISCAS | Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation. | Jinyeong Moon, Byong-Tae Chung |