Can Sitik
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2012–2016
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ISCAS | Exploiting useful skew in gated low voltage clock trees. | Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin |
| 2015 | ISCAS | Enhanced level shifter for multi-voltage operation. | Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin |
| 2014 | ICCD | Timing characterization of clock buffers for clock tree synthesis. | Can Sitik, Scott Lerner, Baris Taskin |
| 2012 | ICCD | Multi-voltage domain clock mesh design. | Can Sitik, Baris Taskin |