| 2024 | MEMOCODE | Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor. | Jeremy Pope, Carl-Johan H. Seger, Henrik Valter |
| 2023 | FDL | Bifrst: Creating Hardware With Building Blocks. | Jeremy Pope, Carl-Johan H. Seger |
| 2021 | FM | Formal Verification of Complex Data Paths: An Industrial Experience. | Carl-Johan H. Seger |
| 2020 | MEMOCODE | Cephalopode: A custom processor aimed at functional language execution for IoT devices. | Jeremy Pope, Jules Saget, Carl-Johan H. Seger |
| 2020 | MEMOCODE | Stately: An FSM Design Tool. | Jeremy Pope, Jules Saget, Carl-Johan H. Seger |
| 2015 | CAV | Word-Level Symbolic Trajectory Evaluation. | Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry |
| 2007 | FMCAD | Automatic Abstraction in Symbolic Trajectory Evaluation. | Sara Adams, Magnus Bjrk, Thomas F. Melham, Carl-Johan H. Seger |
| 2004 | CAV | Compositional Specification and Model Checking in GSTE. | Jin Yang, Carl-Johan H. Seger |
| 2002 | FMCAD | Generalized Symbolic Trajectory Evaluation - Abstraction in Action. | Jin Yang, Carl-Johan H. Seger |
| 2001 | CAV | CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. | John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss |
| 2001 | ICCD | Introduction to Generalized Symbolic Trajectory Evaluation. | Jin Yang, Carl-Johan H. Seger |
| 2000 | CADE | Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice. | Carl-Johan H. Seger |
| 2000 | DAC | Formal verification of iterative algorithms in microprocessors. | Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger |
| 2000 | FMCAD | A Methodology for Large-Scale Hardware Verification. | Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger |
| 2000 | ICFP | Combining functional programming and hardware verification (abstract of invited talk). | Carl-Johan H. Seger |
| 1999 | DAC | Parametric Representations of Boolean Constraints. | Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger |
| 1998 | DAC | Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. | Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger |
| 1998 | FMCAD | Formal Methods in CAD from an Industrial Perspective (abstract). | Carl-Johan H. Seger |
| 1996 | FMCAD | Self-Consistency Checking. | Robert B. Jones, Carl-Johan H. Seger, David L. Dill |
| 1995 | ICCAD | The formal verification of a pipelined double-precision IEEE floating-point multiplier. | Mark D. Aagaard, Carl-Johan H. Seger |
| 1994 | CAV | Composing Symbolic Trajectory Evaluation Results. | Scott Hazelhurst, Carl-Johan H. Seger |
| 1994 | CAV | The Completeness of a Hardware Inference System. | Zheng Zhu, Carl-Johan H. Seger |
| 1994 | ICCD | Automatic Verification of Refinement. | Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger |
| 1993 | DAC | Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. | Jeffrey J. Joyce, Carl-Johan H. Seger |
| 1991 | CAV | A Two-Level Formal Verification Methodology using HOL and COSMOS. | Carl-Johan H. Seger, Jeffrey J. Joyce |
| 1991 | DAC | Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. | Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger |
| 1990 | CAV | Formal Verification of Digital Circuits Using Symbolic Ternary System Models. | Randal E. Bryant, Carl-Johan H. Seger |
| 1989 | ICCAD | A bounded delay race model. | Carl-Johan H. Seger |
| 1986 | ICALP | Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary). | Janusz A. Brzozowski, Carl-Johan H. Seger |