| 2023 | DATE | TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. | Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang, Yu Huang, Jianye Hao |
| 2022 | ICCAD | Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration. | Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng-Ann Heng |
| 2021 | ASPDAC | Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. | Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young |
| 2020 | DAC | CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. | Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young |
| 2019 | ASPDAC | Detailed routing by sparse grid graph and minimum-area-captured path search. | Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young |
| 2019 | ICCAD | Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. | Chak-Wa Pui, Evangeline F. Y. Young |
| 2018 | ASPDAC | A two-step search engine for large scale boolean matching under NP3 equivalence. | Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young |
| 2017 | ICCAD | Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). | Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu |
| 2016 | DAC | Legalization algorithm for multiple-row height standard cell design. | Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young |
| 2016 | ICCAD | RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. | Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu |