Chang-Tzu Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
4
Active years
2002–2019
Best venue rank
B
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ISCAS | More Effective Power Network Prototyping by Analytical and Centroid Learning. | Yu-Hsiang Chuang, Chang-Tzu Lin, Hung-Ming Chen, Chi-Han Lee, Ting-Sheng Chen |
| 2017 | ASPDAC | Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. | Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou |
| 2014 | ICCD | Improving power delivery network design by practical methodologies. | Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai |
| 2013 | ASPDAC | I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. | Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai |
| 2013 | DATE | Effective power network prototyping via statistical-based clustering and sequential linear programming. | Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee |
| 2010 | ASPDAC | CAD reference flow for 3D via-last integrated circuits. | Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu |
| 2007 | ISCAS | Noise-Aware Floorplanning for Fast Power Supply Network Design. | Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng |
| 2005 | ISCAS | Modem floorplanning with abutment and fixed-outline constraints. | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang, Hsin-Hsien Ho |
| 2004 | ASPDAC | Robust fixed-outline floorplanning through evolutionary search. | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang |
| 2003 | ASPDAC | Non-slicing floorplans with boundary constraints using generalized polish expression. | De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang |
| 2002 | ICCD | GPE: A New Representation for VLSI Floorplan Problem. | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang |