Chao-Hsuan Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2019–2020
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | ICCD | Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. | Chao-Hsuan Huang, Ishan G. Thakkar |
| 2019 | CASES | Mitigating Write Disturbance in Phase Change Memory Architectures. | Chao-Hsuan Huang, Ishan G. Thakkar |