Chau-Chin Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
3
Active years
2013–2020
Best venue rank
A*
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | DAC | Latch Clustering for Timing-Power Co-Optimization. | Chau-Chin Huang, Gustavo E. Tllez, Gi-Joon Nam, Yao-Wen Chang |
| 2017 | DAC | Graph-Based Logic Bit Slicing for Datapath-Aware Placement. | Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang |
| 2017 | ICCAD | Clock-aware placement for large-scale heterogeneous FPGAs. | Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo |
| 2016 | DAC | Timing-driven cell placement optimization for early slack histogram compression. | Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo |
| 2015 | ASPDAC | Detailed-Routing-Driven analytical standard-cell placement. | Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang |
| 2015 | ICCAD | Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. | Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang |
| 2014 | DAC | Routability-Driven Blockage-Aware Macro Placement. | Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang |
| 2013 | DAC | Routability-driven placement for hierarchical mixed-size circuit designs. | Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang |