| 2007 | ISCAS | Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. | Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen |
| 2006 | ASPDAC | A 52mW 1200MIPS compact DSP for multi-core media SoC. | Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen |
| 2006 | ISCAS | Programmable FIR filter with adder-based computing engine. | Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen |
| 2005 | ISCAS | Pipelining technique for energy-aware datapaths. | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
| 2005 | ISCAS | Hierarchical instruction encoding for VLIW digital signal processors. | Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen |
| 2004 | ASPDAC | A bandwidth and memory efficient MPEG-4 shape encoder. | Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen |
| 2004 | ISCAS | Trace-path analysis and performance estimation for multimedia application in embedded system. | Nelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen |
| 2004 | ISCAS | QME: an efficient subsampling-based block matching algorithm for motion estimation. | Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen |
| 2004 | ISCAS | A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. | Kun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen |
| 2004 | ISCAS | A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. | Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen |
| 2004 | ISCAS | Static floating-point unit with implicit exponent tracking for embedded DSP. | Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen |
| 2003 | ICCD | An Efficient VLIW DSP Architecture for Baseband Processing. | Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen |
| 2003 | ISCAS | A memory efficient realization of cyclic convolution and its application to discrete cosine transform. | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
| 2003 | ISCAS | Area-effective FIR filter design for multiplier-less implementation. | Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen |
| 2002 | ISCAS | A new group distributed arithmetic design for the one dimensional discrete Fourier transform. | Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen |
| 2002 | ISCAS | High-speed memory-saving architecture for the embedded block coding in JPEG2000. | Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen |
| 2002 | ISCAS | CASCADE - configurable and scalable DSP environment. | Tay-Jyi Lin, Chein-Wei Jen |
| 2001 | ISCAS | Power modeling and low-power design of content addressable memories. | Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen |
| 2001 | ISCAS | Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing. | Yuan-Chung Lee, Chein-Wei Jen |
| 2001 | ISCAS | An efficient 2-D DWT architecture via resource cycling. | Tay-Jyi Lin, Chein-Wei Jen |
| 2000 | GMP | On-Line Polygon Refining Using a Low Computation Subdivision Algorithm. | Yuan-Chung Lee, Chein-Wei Jen |
| 2000 | ICASSP | A high performance carry-save to signed-digit recoder for fused addition-multiplication. | Wen-Chang Yeh, Chein-Wei Jen |
| 2000 | ISCAS | A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers. | Ilion Yi-Liang Hsiao, Chein-Wei Jen |
| 2000 | ISCAS | Deferred lighting: a computation-efficient approach for real-time 3-D graphics. | Bor-Sung Liang, Wen-Chang Yeh, Yuan-Chung Lee, Chein-Wei Jen |
| 2000 | ISCAS | Motion estimation using on-line arithmetic. | Ching-Long Su, Chein-Wei Jen |
| 1998 | ICASSP | Low power FIR filter realization with differential coefficients and input. | Tian-Sheuan Chang, Chein-Wei Jen |
| 1996 | ICIP | A programmable concurrent video signal processor. | Chih-Chin Chen, Chein-Wei Jen |
| 1994 | ICASSP | A novel VLSI array design for the discrete Hartley transform using cyclic convolution. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1994 | ISCAS | A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1993 | ISCAS | A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1993 | ISCAS | A Multi-phase Shared Bus Structure for the Fast Fourier Transform. | Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen |
| 1993 | ISCAS | A High Throughput Systolic Design for QR Algorithm. | Jiann-Jenn Wang, Chein-Wei Jen |
| 1992 | ICASSP | A memory-based approach to design and implement systolic arrays for DFT and DCT. | Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen |
| 1992 | ICASSP | Efficient synthesis and high-speed implementation of look-ahead recursive filters. | Chien-Piao Lan, Shih-Chieh Wen, Chein-Wei Jen |
| 1991 | ICASSP | A high-level synthesizer for VLSI array architectures dedicated to digital signal processing. | Tung-Hao Huang, Chi-Min Liu, Chein-Wei Jen |
| 1990 | ICASSP | Parallel adaptive algorithm for moving target indicator and its VLSI array realization. | Chi-Min Liu, Bor-Shyong Yang, Chein-Wei Jen |
| 1989 | ICASSP | Two-level pipeline design for image resampling. | Chein-Wei Jen, Chi-Min Liu |
| 1986 | RTSS | Real-Time Configuration for Fault-Tolerant VLSI Array Processors. | Sun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen |