Cheng-Liang Hung
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2007–2012
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ISCAS | A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-m CMOS technology. | Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng |
| 2008 | DDECS | A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. | Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw |
| 2007 | ISCAS | A Sub-1V Low-Power High-Speed Static Frequency Divider. | Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su |