Chengbo Xue
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
2017–2019
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ISCAS | A Pre-RTL Simulator for Neural Networks. | Shan Cao, Zhenyi Bao, Chengbo Xue, Wei Deng, Shugong Xu, Shunqing Zhang |
| 2018 | ISCAS | A Fast Modular Inversion FPGA Implementation over GF(2 | Jiakun Li, Zhe Li, Chengbo Xue, Jingqi Zhang, Wei Gao, Shan Cao |
| 2018 | ISCAS | A Reconfigurable Pipelined Architecture for Convolutional Neural Network Acceleration. | Chengbo Xue, Shan Cao, Rongkun Jiang, Hao Yang |
| 2017 | ISCAS | A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips. | Lei Zhang, Jianxun Yang, Chengbo Xue, Yue Ma, Shan Cao |