Chi-Heng Yang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2012–2017
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ITW | 3X endurance enhancement by advanced signal processor for 3D NAND flash memory. | Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Yu-Siang Yang, Szu-Wei Chen, Chun-Wei Tsao, An-Chang Liu, Lih-Yuarn Ou, Tien-Ching Wang, Shao-Wei Yen, Yu-Hsiang Lin, Kuo-Hsin Lai, Chi-Heng Yang, Li-Chun Liang, Pei-Jung Hsu |
| 2012 | ICASSP | A fully parallel BCH codec with double error correcting capability for NOR flash applications. | Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang |