Chi-Sheng Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
2002–2010
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | ISCAS | High-speed and low-power programmable frequency divider. | Ting-Hsu Chien, Chi-Sheng Lin, Chin-Long Wey, Ying-Zong Juang, Chun-Ming Huang |
| 2010 | ISCAS | An effective phase detector for phase-locked loops with wide capture range and fast acquisition time. | Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey |
| 2010 | VTC | Novel Channel Estimation Techniques in IEEE 802.11p Environments. | Chi-Sheng Lin, Jia-Chin Lin |
| 2004 | ISLPED | A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. | Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu |
| 2003 | ISCAS | Low-power and low-voltage fully parallel content-addressable memory. | Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu |
| 2002 | ISCAS | Design of a pipelined and expandable sorting architecture with simple control scheme. | Chi-Sheng Lin, Bin-Da Liu |
| 2002 | ISCAS | A scalable sorting architecture based on maskable WTA/MAX circuit. | Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu |