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Chia-Hsiang Yang

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

4

Active years

2004–2021

Best venue rank

B

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2021ICASSPA Color Doppler Processing Engine with an Adaptive Clutter Filter for Portable Ultrasound Imaging Devices.Yi-Lin Lo, Chia-Hsiang Yang
2020GLOBECOMIterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax.Yao-Pin Wang, Chi-Chih Wen, Chen-Chien Kao, Chung-Jung Huang, Der-Zheng Liu, Chia-Hsiang Yang
2020ISCASA CycleGAN Accelerator for Unsupervised Learning on Mobile Devices.Yi-Yen Hsieh, Yu-Chi Lee, Chia-Hsiang Yang
2018ISCASA 22-1616 Reconfigurable GGMD Processor for MIMO Communication Systems.Chih-Hsuan Chiang, Shuo-An Huang, Chiao-En Chen, Chia-Hsiang Yang
2017ISCASIntegration of energy-recycling logic and wireless power transfer for ultra-low-power implantables.Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang
2017VTCAn Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors.Wei-Cheng Sun, Chia-Hsiang Yang, Yen-Ming Chen, Yeong-Luh Ueng
2016ICASSPError-resilient sequential cells with successive time borrowing for stochastic computing.Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou
2011GLOBECOMA Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection.Fang-Li Yuan, Chia-Hsiang Yang, Dejan Markovic
2011GLOBECOMAn Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing.Tsung-Han Yu, Chia-Hsiang Yang, Dejan Markovic, Danijela Cabric
2008GLOBECOMA Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications.Chia-Hsiang Yang, Dejan Markovic
2004ISCASDesign of a low-complexity receiver for impulse-radio ultra-wideband communication systems.Chia-Hsiang Yang, Yu-Hsuan Lin, Shih-Chun Lin, Tzi-Dar Chiueh