| 2026 | ISCAS | A 6-bit 2.15-GS/s 1.05-mW Flash-Assisted Time-Domain ADC with 0.8-V supply. | Utkarsh Sharma, Behzad Razavi, Chih-Kong Ken Yang |
| 2022 | ISCAS | A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input. | Jiazhang Song, Li-Yang Chen, Mau-Chung Frank Chang, Sudhakar Pamarti, Chih-Kong Ken Yang |
| 2021 | ISCAS | A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. | Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen |
| 2015 | CLOSER | Effects of Active Cooling on Workload Management in High Performance Processors. | Won Ho Park, Chih-Kong Ken Yang |
| 2014 | ISCAS | A compact stacked-device output driver in low-voltage CMOS Technology. | Yousr Ismail, Chih-Kong Ken Yang |
| 2013 | ISCAS | A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. | Ramy Yousry, Henry Park, E-Hung Chen, Chih-Kong Ken Yang |
| 2010 | HOTI | Clocking Links in Multi-chip Packages: A Case Study. | Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho |
| 2009 | DAC | A stochastic jitter model for analyzing digital timing-recovery circuits. | James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi |
| 2007 | ICCAD | Device-circuit co-optimization for mixed-mode circuit design via geometric programming. | Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang |
| 2006 | DAC | Power-centric design of high-speed I/Os. | Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang |