Chih-Pin Su
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
2002–2005
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ASPDAC | A configurable AES processor for enhanced security. | Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | ASPDAC | Design and test of a scalable security processor. | Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2004 | ASPDAC | An HMAC processor with integrated SHA-1 and MD5 algorithms. | Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | ASPDAC | A highly efficient AES cipher chip. | Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | ASPDAC | Design of a scalable RSA and ECC crypto-processor. | Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu |
| 2002 | DATE | A Hierarchical Test Scheme for System-On-Chip Designs. | Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin |