| 2024 | ICASSP | Multi-Layer Relation Knowledge Distillation For Fingerprint Restoration. | Yu-Min Chiu, Ching-Te Chiu, Dao-Heng Luo |
| 2024 | ISCAS | Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction. | Yi-Fan Chen, Yu-Jen Chang, Ching-Te Chiu, Ming-Long Huang, Geng-Ming Liang, Chao-Lin Lee, Jenq-Kuen Lee, Ping-Yu Hsieh, Wei-Chih Lai |
| 2024 | ISCAS | Feature Points based Residual UNet with Nonlinear Decay Rate for Partial Wet Fingerprint Restoration and Recognition. | An-Ting Hsieh, Ching-Te Chiu, Tsai-Chieh Chen, Mao-Hsiu Hsu, Wenyong Long |
| 2023 | ICASSP | RGB-D Based Pose-Invariant Face Recognition Via Attention Decomposition Module. | Wei-Chen Lin, Ching-Te Chiu, Kuan-Chang Shih |
| 2022 | ISCAS | RGBD-based Hardware Friendly Head Pose Estimation System via Convolutional attention module. | Yen-Yu Cheng, Ching-Te Chiu, Yi-Fan Chen |
| 2022 | ISCAS | Multi-View RGB-D Based 3D Point Cloud Face Model Reconstruction System. | Jie-Yu Luo, Ching-Te Chiu, An-Ting Hsieh |
| 2021 | ISCAS | High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. | Kuan-Ting Lin, Ching-Te Chiu, Jheng-Yi Chang, Shan-Chien Hsiao |
| 2020 | ICASSP | Fast Single-View 3D Object Reconstruction with Fine Details Through Dilated Downsample and Multi-Path Upsample Deep Neural Network. | Chia-Ho Hsu, Ching-Te Chiu, Chia-Yu Kuan |
| 2020 | ICASSP | Object Detection with Color and Depth Images with Multi-Reduced Region Proposal Network and Multi-Pooling. | Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng |
| 2020 | ICASSP | Rgb-D Based Multi-Modal Deep Learning for Face Identification. | Tzu-Ying Lin, Ching-Te Chiu, Ching-Tung Tang |
| 2020 | ICASSP | Depth Estimation From Single Image Through Multi-Path-Multi-Rate Diverse Feature Extractor. | Wen-Yi Lo, Ching-Te Chiu, Jie-Yu Luo |
| 2020 | ICASSP | Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. | Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang |
| 2019 | ICASSP | Real-time Object Detection via Pruning and a Concatenated Multi-feature Assisted Region Proposal Network. | Kuan-Hung Shih, Ching-Te Chiu, Yen-Yu Pu |
| 2019 | ICASSP | Multi-teacher Knowledge Distillation for Compressed Video Action Recognition on Deep Neural Networks. | Meng-Chieh Wu, Ching-Te Chiu, Kun-Hsuan Wu |
| 2019 | ICIP | An Energy-Aware Bit-Serial Streaming Deep Convolutional Neural Network Accelerator. | Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin |
| 2018 | ICASSP | PVDC: A Binary Descriptor Using Pore-Valley Disk Code Structure for High-Resolution Partial Fingerprint Recognition. | Pei-Yin Chou, Ching-Te Chiu |
| 2018 | ICASSP | Resource Efficient Hardware Implementation for Real-Time Traffic Sign Recognition. | Huai-Mao Weng, Ching-Te Chiu |
| 2017 | ICASSP | LBP edge-mapped descriptor using MGM interest points for face recognition. | Jou Lin, Ching-Te Chiu |
| 2017 | ICASSP | Motion clustering with hybrid-sample-based foreground segmentation for moving cameras. | Yi-Chan Wu, Ching-Te Chiu |
| 2017 | ISCAS | Single image super-resolution using hybrid patch search and local self-similarity. | Shen-Li Lo, Ching-Te Chiu |
| 2016 | ICASSP | A cost-effective minutiae disk code for fingerprint recognition and its implementation. | Tsai-Te Chu, Ching-Te Chiu |
| 2016 | ICASSP | Fingerprint recognition with ridge features and minutiae on distortion. | Chu-Chiao Liao, Ching-Te Chiu |
| 2016 | ISCAS | Binary descriptor based SIFT and hardware implementation. | Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu |
| 2015 | ICASSP | Local binary pattern orientation based face recognition. | Yi-Kang Shen, Ching-Te Chiu |
| 2015 | ISCAS | Accelerating AdaBoost algorithm using GPU for multi-object recognition. | Pin Yi Tsai, Yarsun Hsu, Ching-Te Chiu, Tsai-Te Chu |
| 2014 | ICASSP | Boosted multi-class object detection with parallel hardware implementation for real-time applications. | Yao-Tsung Yang, Ching-Te Chiu |
| 2013 | ICASSP | Depth-based posture recognition by radar and vision fusion for real-time applications. | I-Cheng Tsai, Ching-Te Chiu |
| 2013 | ICIP | Edge curve scaling and smoothing with cubic spline interpolation. | Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu |
| 2012 | HPCC | A Study of NoC Topologies and Switching Arbitration Mechanisms. | Yung-Chang Chang, Ching-Te Chiu |
| 2012 | ICASSP | A 5.8 Gbps uniform mapping data center switch. | Wei-Chih Lai, Ching-Te Chiu |
| 2012 | ISCAS | A novel low gate-count serializer topology with Multiplexer-Flip-Flops. | Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao |
| 2011 | ASPDAC | On the design and analysis of fault tolerant NoC architecture using spare routers. | Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu |
| 2011 | ASPDAC | A 32Gbps low propagation delay 44 switch IC for feedback-based system in 0.13μm CMOS technology. | Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu |
| 2011 | GLOBECOM | Handover Delay Reduction and Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone. | Sih-Kai Li, Jen-Shun Yang, Ching-Te Chiu, Po-Ting Yeh, Jenq-Neng Hwang |
| 2011 | ICIP | Curve-based and image-based JND contrast analysis for inverse tone mapping operators. | Chih-Rung Chen, Ching-Te Chiu |
| 2011 | ICIP | Texture classification based low order local binary pattern for face recognition. | Ching-Te Chiu, Cyuan-Jhe Wu |
| 2011 | ICIP | Low visual difference virtual high dynamic range image synthesizer from a single legacy image. | Tsun-Hsien Wang, Ching-Te Chiu |
| 2011 | ISCAS | A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. | Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu |
| 2010 | ICASSP | Switching bilateral filter with a texture/noise detector for universal noise removal. | Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu |
| 2010 | ISCAS | A 32Gbps low propagation delay 44 switch IC for feedback-based system in 0.13μm CMOS technology. | Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu |
| 2010 | ISCAS | Hardware-efficient image enhancement with bilateral tone adjustment. | Wei-Ming Ke, Ching-Te Chiu |
| 2010 | ISCAS | A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification. | Chih-Hsing Lin, Yung-Chang Chang, Wen-Chih Huang, Wei-Chih Lai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Chun-Ming Huang, Chih-Chyau Yang, Shih-Lun Chen |
| 2010 | ISCAS | A novel MUX-FF circuit for low power and high speed serial link interfaces. | Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
| 2009 | ICIP | Hardware-efficient virtual high dynamic range image reproduction. | Wei-Ming Ke, Tsun-Hsien Wang, Ching-Te Chiu |
| 2009 | ICIP | A 100MHz hardware-efficient boost cascaded face detection design. | Wei-Su Wong, Chih-Rung Chen, Ching-Te Chiu |
| 2008 | ICIP | Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. | Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay |
| 2008 | ISCAS | A 28Gbps 44 switch with low jitter SerDes using area-saving RF model in 0.13m CMOS technology. | Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
| 2007 | ASPDAC | A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. | Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu |
| 2007 | ICIP | Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications. | Tsun-Hsien Wang, Wei-Ming Ke, Ding-Chuang Zwao, Fang-Chu Chen, Ching-Te Chiu |
| 2007 | ICIP | Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video. | Tsun-Hsien Wang, Wei-Su Wong, Fang-Chu Chen, Ching-Te Chiu |
| 2007 | ISCAS | A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. | Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
| 2007 | ISCAS | A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. | Chih-Hsing Lin, Ching-Te Chiu |
| 2006 | NCA | A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS. | Hou-Cheng Tzeng, Ching-Te Chiu |
| 2005 | GLOBECOM | Design a simple and high performance switch using a two-stage architecture. | Chih-Ying Tu, Cheng-Shang Chang, Duan-Shin Lee, Ching-Te Chiu |
| 1993 | ICASSP | Optimal unified IIR architectures for time-recursive discrete sinusoidal transforms. | Kuo J. Ray Liu, Ching-Te Chiu, Ravi K. Kolagotla, Joseph F. JJ |