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Chongyan Gu

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

18

Venues

6

Active years

2014–2025

Best venue rank

A*

Where they publish

Papers

18 indexed papers, newest first.

YearVenueTitleAuthors
2025CASESSpecial Sessions - Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond.Siva Satyendra Sahoo, Bastien Deveautour, Marcello Traiola, Chongyan Gu, Yun Wu, Aditya Japa, Salim Ullah, Akash Kumar
2025DACSecurity of Approximate Neural Networks against Power Side-channel Attacks.Aditya Japa, Jack Miskelly, Mire O'Neill, Chongyan Gu
2025ICCADInvited Paper: Rowhammer Mitigation by Approximate Computing: A Compressed Sensing Case Study.Yuhang Hao, Yun Wu, Minmin Jiang, Mire O'Neill, Chongyan Gu
2025ISCASAxRA: Approximate Rowhammer Attack for Modern DRAM Systems.Yuhang Hao, Yun Wu, Ziying Ni, Jack Miskelly, Mire O'Neill, Chongyan Gu
2024ISCASNegative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices.Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi
2024ISCASA Novel Methodology for Processor based PUF in Approximate Computing.Aditya Japa, Jack Miskelly, Yijun Cui, Mire O'Neill, Chongyan Gu
2023ISCASNovel Intrinsic Physical Unclonable Function Design for Post-quantum Cryptography.Baosheng Wang, Yijun Cui, Chongyan Gu, Chenghua Wang, Weiqiang Liu
2021ISCASA Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.Hu Zhang, Chenghua Wang, Chenggang Yan, Yijun Cui, Chongyan Gu, Mire O'Neill, Weiqiang Liu
2020ISCASProgrammable Ring Oscillator PUF Based on Switch Matrix.Yijun Cui, Yunpeng Chen, Chenghua Wang, Chongyan Gu, Mire O'Neill, Weiqiang Liu
2020ISCASA Novel Feature Extraction Strategy for Hardware Trojan Detection.Shichao Yu, Chongyan Gu, Weiqiang Liu, Mire O'Neill
2019CCSA Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Mire O'Neill
2019CCSSCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption.Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
2019ISCASTheoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement.Yale Wang, Chenghua Wang, Chongyan Gu, Yijun Cui, Mire O'Neill, Weiqiang Liu
2019ISCASMulti-Incentive Delay-Based (MID) PUF.Zhengran Zhang, Chongyan Gu, Yijun Cui, Chuan Zhang, Mire O'Neill, Weiqiang Liu
2018ASPDACA machine learning attack resistant multi-PUF design on FPGA.Qingqing Ma, Chongyan Gu, Neil Hanley, Chenghua Wang, Weiqiang Liu, Mire O'Neill
2017ISCASFPGA-based strong PUF with increased uniqueness and entropy properties.Chongyan Gu, Neil Hanley, Mire O'Neill
2015ISCASUltra-compact and robust FPGA-based PUF identification generator.Chongyan Gu, Mire O'Neill
2014ISCASA unique and robust single slice FPGA identification generator.Chongyan Gu, Julian P. Murphy, Mire O'Neill