Chun-Po Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
2010–2018
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ISCAS | A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window. | Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang |
| 2017 | ISCAS | A 12-bit 40-MS/s calibration-free SAR ADC. | Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang |
| 2016 | ISCAS | A pipeline ADC with latched-based ring amplifiers. | Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, Soon-Jyh Chang |
| 2012 | ISCAS | A power-efficient sizing methodology of SAR ADCs. | Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin |
| 2011 | DAC | Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. | Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang |
| 2010 | DAC | Performance-driven analog placement considering boundary constraint. | Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang |