| 2016 | ASPDAC | Automatic abstraction refinement of TR for PDR. | Kuan Fan, Ming-Jen Yang, Chung-Yang (Ric) Huang |
| 2014 | ASPDAC | Adaptive interpolation-based model checking. | Chien-Yu Lai, Cheng-Yin Wu, Chung-Yang (Ric) Huang |
| 2013 | DAC | A robust constraint solving framework for multiple constraint sets in constrained random verification. | Bo-Han Wu, Chung-Yang (Ric) Huang |
| 2013 | DAC | A counterexample-guided interpolant generation algorithm for SAT-based model checking. | Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang |
| 2013 | ICCAD | Conquering the scheduling alternative explosion problem of SystemC symbolic simulation. | Chun-Nan Chou, Chen-Kai Chu, Chung-Yang (Ric) Huang |
| 2012 | DAC | Symbolic model checking on SystemC designs. | Chun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, Chung-Yang (Ric) Huang |
| 2012 | ICCAD | A robust general constrained random pattern generator for constraints with variable ordering. | Bo-Han Wu, Chung-Yang (Ric) Huang |
| 2012 | TACAS | QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification. | Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang |
| 2011 | DAC | Using SAT-based Craig interpolation to enlarge clock gating functions. | Ting-Hao Lin, Chung-Yang (Ric) Huang |
| 2011 | DAC | Interpolation-based incremental ECO synthesis for multi-error logic rectification. | Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang |
| 2011 | ICCAD | Match and replace - A functional ECO engine for multi-error circuit rectification. | Shao-Lun Huang, Wei-Hsun Lin, Chung-Yang (Ric) Huang |