Claudio Passerone
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
23
Venues
10
Active years
1995–2025
Best venue rank
A*
Where they publish
Papers
23 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DAC | LA-MTL: Latency-Aware Automated Multi-Task Learning. | Shambhavi Balamuthu Sampath, Sami Sawani, Moritz Thoma, Lukas Frickenstein, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Claudio Passerone, Walter Stechele |
| 2025 | DATE | HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization. | Shambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2024 | CVPR | Pruning as a Binarization Technique. | Lukas Frickenstein, Pierpaolo Mor, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Claudio Passerone, Walter Stechele |
| 2024 | DATE | MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. | Pierpaolo Mor, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2024 | WACV | Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge. | Pierpaolo Mor, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2023 | DAC | WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration. | Pierpaolo Mor, Shambhavi Balamuthu Sampath, Lukas Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Walter Stechele, Claudio Passerone |
| 2022 | DAC | Accelerating and pruning CNNs for semantic segmentation on FPGA. | Pierpaolo Mor, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone |
| 2007 | DSD | Architecture of a Small Low-Cost Satellite. | Dante Del Corso, Claudio Passerone, Leonardo Maria Reyneri, Claudio Sanso, Marco Borri, Stefano Speretta, Maurizio Tranchero |
| 2006 | ISCAS | Real time operating system modeling in a system level design environment. | Claudio Passerone |
| 2005 | DATE | A Time Slice Based Scheduler Model for System Level Design. | Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe |
| 2004 | DATE | Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform. | Alberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno |
| 2004 | DSD | An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design. | Ivan Blunno, Guy Alain Narboni, Claudio Passerone |
| 2003 | DATE | Hardware/Software Design Space Exploration for a Reconfigurable Processor. | Alberto La Rosa, Luciano Lavagno, Claudio Passerone |
| 2002 | DATE | False Path Elimination in Quasi-Static Scheduling. | G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe |
| 2002 | EMSOFT | Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. | Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe |
| 2001 | CASES | A software development tool chain for a reconfigurable processor. | Alberto La Rosa, Luciano Lavagno, Claudio Passerone |
| 2001 | DATE | Generation of minimal size code for scheduling graphs. | Claudio Passerone, Yosinori Watanabe, Luciano Lavagno |
| 2000 | DAC | Task generation and compile-time scheduling for mixed data-control embedded software. | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli |
| 1999 | DATE | Computing Timed Transition Relations for Sequential Cycle-Based Simulation. | Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer |
| 1998 | DAC | A Case Study in Embedded System Design: An Engine Control Unit. | Tullio Cuatto, Claudio Passerone, Luciano Lavagno, Attila Jurecska, Antonino Damiano, Claudio Sanso, Alberto L. Sangiovanni-Vincentelli |
| 1997 | ASPDAC | Trade-off evaluation in embedded system design via co-simulation. | Claudio Passerone, Luciano Lavagno, Claudio Sanso, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli |
| 1997 | DAC | Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis. | Claudio Passerone, Luciano Lavagno, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli |
| 1995 | PDP | Using a massively parallel architecture for integrated circuits testing. | Francesco Gregoretti, Claudio Passerone |