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Daejin Park

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

17

Venues

11

Active years

2015–2025

Best venue rank

A*

Where they publish

Papers

17 indexed papers, newest first.

YearVenueTitleAuthors
2025IECONLightweight Empirical Reinforcement Learning Driven Adaptive Super-Twisting Control with Fused Linear-Nonlinear Sliding Surfaces for Embedded Vehicle Control.Hyunjoong Lee, Daejin Park
2024COMPSACCloud Memory Enabled Code Generation via Online Computing for Seamless Edge AI Operation.Myeongjin Kang, Daejin Park
2024COMPSACImplementation of Dynamic Round Robin Scheduling on Bare-Metal Shallow Multi-OS for Lightweighted Microcontrollers.Minjung Kim, Daejin Park
2024PERCOMDeep Learning based Human Detection using Thermal-RGB Data Fusion for Safe Automotive Guided-Driving.Heuijee Yun, Daejin Park
2024TenconOptimizing Multithreaded Access to Global Variables in SPM through Compiler-Enhanced Dependency Analysis.Gihyeon Jeon, Daejin Park
2023EMSOFTWork-in-Progress: Searching Optimal Compiler Optimization Passes Sequence for Reducing Runtime Memory Profile using Ensemble Reinforcement Learning.Juneseo Chang, Daejin Park
2023EMSOFTWork-in-Progress: Micro-Accelerator-in-the-Loop Framework for MCU Integrated Accelerator Peripheral Fast Prototyping.Jisu Kwon, Daejin Park
2023IECONRTOS-Based Task-Driven Scheduling for Vehicle Independent Brushless Direct Current Motor Control.Dongkyu Jung, Daejin Park
2022EMSOFTWork-in-Progress: Accuracy-Area Efficient Online Fault Detection for Robust Neural Network Software-Embedded Microcontrollers.Juneseo Chang, Sejong Oh, Daejin Park
2021ISCASMetamorphic Edge Processor Simulation Framework Using Flexible Runtime Partial Replacement of Software-Embedded Verilog RTL Models.Jisu Kwon, Sejong Oh, Daejin Park
2020PADSRuntime Abstraction-Level Conversion of Discrete-Event Wafer-fabrication Models for Simulation Acceleration.Moon Gi Seok, Chew Wye Chan, Wentong Cai, Hessam S. Sarjoughian, Daejin Park
2019ASPDACA high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs.Moon Gi Seok, Hessam S. Sarjoughian, Daejin Park
2019DASCEnergy-Efficient Signal Processors with Silent Mirror Tracer for Long-Term Activity Monitoring.Jaeyong Jung, Jeonghun Cho, Daejin Park
2019DASCLightweight Polygonal Approximation-Based ECG Signal Processing Platform.Junho Kwak, Seungmin Lee, Jeonghun Cho, Daejin Park
2019DASCReconfigurable Fault-Safe Processor Platform Based on RISC-V for Large-Scaled IoT-Driven Applications.Hyeongyun Moon, Jeonghun Cho, Daejin Park
2015FNCLow-Power Universal Edge Tracer Architecture using Accuracy-Controlled Resource Reallocation for Event-Driven Sensing Applications.Daejin Park, Jeonghun Cho
2015UICEfficient Frequency and Duty Cycle Control Method for Fast Pulse-Charging of Distributed Battery Packs by Sharing Cell Status.Meng Di Yin, Jiae Youn, Daejin Park, Jeonghun Cho