| 2014 | FMCAD | Post-silicon timing diagnosis made simple using formal technology. | Daher Kaiss, Jonathan Kalechstain |
| 2009 | FMCAD | A compositional theory for post-reboot observational equivalence checking of hardware. | Zurab Khasidashvili, Daher Kaiss, Doron Bustan |
| 2007 | FMCAD | Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. | Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili |
| 2006 | FMCAD | Post-reboot Equivalence and Compositional Verification of Hardware. | Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna |
| 2006 | ICCD | Seqver : A Sequential Equivalence Verifier for Hardware Designs . | Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili |
| 2006 | LPAR | Boolean Rings for Intersection-Based Satisfiability. | Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss |
| 2004 | ICCAD | Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. | Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna |
| 2004 | SAT | Boolean Ring Satisfiability. | Nachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss |
| 2001 | CAV | CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. | John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss |