Daisuke Nakatsu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2010–2010
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | DATE | Power Variance Analysis breaks a masked ASIC implementation of AES. | Yang Li, Kazuo Sakiyama, Lejla Batina, Daisuke Nakatsu, Kazuo Ohta |
| 2010 | WISA | Combination of SW Countermeasure and CPU Modification on FPGA against Power Analysis. | Daisuke Nakatsu, Yang Li, Kazuo Sakiyama, Kazuo Ohta |