| 2025 | CBMS | Genetic Algorithm-Optimized Apodization for Ultrafast Plane-Wave Compounding. | Zahraa Alzein, Daniele D. Caviglia |
| 2025 | CBMS | A Multi-Objective Optimization Framework for Compound Weights in Divergent Wave Ultrasound Imaging. | Zahraa Alzein, Daniele D. Caviglia |
| 2025 | ISCAS | Live Demonstration: Sea Wave Energy Harvester for Environmental Monitoring Buoys. | Filippo Nicora, Orazio Aiello, Corrado Boragno, Daniele D. Caviglia, Alessandro Lo Schiavo |
| 2024 | ISCAS | Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages. | Duy-Hieu Bui, Duc-Manh Tran, Daniele D. Caviglia, Orazio Aiello |
| 2024 | ISCAS | 0.5V 32nW Inverter-Based Gm-C Filter for Bio-Signal Processing. | Ali Namdari, Orazio Aiello, Daniele D. Caviglia |
| 2023 | ICASSP | Opportunistic Rainfall Sensing: State of the Art and Perspectives in Italy. | Filippo Giannetti, Vincenzo Lottici, Fabiola Sapienza, F. Porc, Giacomo Roversi, P. P. Alberoni, Erika Covi, Roberto Nebuloni, Greta Cazzaniga, Carlo De Michele, Cristina Deidda, Matteo Colli, Sara Zani, Christian Gianoglio, Daniele D. Caviglia, Elisa Adirosi |
| 2000 | IJCNN | An On-Chip Learning Neural Network. | Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle |
| 2000 | IJCNN | A VLSI Architecture for Weight Perturbation on Chip Learning Implementation. | Francesco Diotalevi, Maurizio Valle, Gian Marco Bo, Daniele D. Caviglia |
| 2000 | IJCNN | Evaluation of Gradient Descent Learning Algorithms with an Adaptive Local Rate Technique for Hierarchical Feed Forward Architectures. | Francesco Diotalevi, Maurizio Valle, Daniele D. Caviglia |
| 2000 | ISCAS | An analog on-chip learning circuit architecture of the weight perturbation algorithm. | Francesco Diotalevi, Maurizio Valle, Gian Marco Bo, Ezio Biglieri, Daniele D. Caviglia |
| 2000 | ISCAS | Analog CMOS current mode neural primitives. | Francesco Diotalevi, Maurizio Valle, Gian Marco Bo, Enrico Biglieri, Daniele D. Caviglia |
| 1999 | IWANN | Gradient Descent Learning Algorithm for Hierarchical Neural Networks: A Case Study in Industrial Quality. | Daniela Baratta, Francesco Diotalevi, Maurizio Valle, Daniele D. Caviglia |
| 1997 | ICANN | A Hardware Implementation of Hierarchical Neural Networks for Real-Time Quality Contol Systems in Industrial Applications. | Daniela Baratta, Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle, Giovanni Canepa, Riccardo Parenti, Carla Penno |
| 1995 | DATE | An ASIC design for real-time image processing in industrial applications. | Maurizio Valle, Giovanni Nateri, Daniele D. Caviglia, Giacomo M. Bisio, Luciano Briozzo |
| 1990 | IJCNN | Effects of weight discretization on the back propagation learning method: algorithm design and hardware realization. | Daniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio |
| 1989 | ICASSP | Neural networks on a transputer array. | Ermanno Di Zitti, Daniele D. Caviglia, Giacomo M. Bisio, Giancarlo Parodi |