| 2017 | DAC | Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. | Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery |
| 2017 | ICCAD | Rapid gate sizing with fewer iterations of Lagrangian Relaxation. | Ankur Sharma, David G. Chinnery, Shrirang Dhamdhere, Chris Chu |
| 2015 | ICCAD | Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. | Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu |
| 2005 | DAC | Closing the power gap between ASIC and custom: an ASIC perspective. | David G. Chinnery, Kurt Keutzer |
| 2005 | ISLPED | Linear programming for sizing, V | David G. Chinnery, Kurt Keutzer |
| 2003 | ICCD | Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. | Masayuki Ito, David G. Chinnery, Kurt Keutzer |
| 2003 | ISLPED | Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. | David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer |
| 2001 | DAC | Achieving 550Mhz in an ASIC Methodology. | David G. Chinnery, Borivoje Nikolic, Kurt Keutzer |
| 2001 | ICCD | A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. | Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer |
| 2000 | DAC | Closing the gap between ASIC and custom: an ASIC perspective. | David G. Chinnery, Kurt Keutzer |