David M. Russinoff
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2000–2022
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ARITH | Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking. | David M. Russinoff, Javier D. Bruguera, Cuong Chau, Mayank Manjrekar, Nicholas Pfister, Harsha Valsaraju |
| 2007 | CAV | A Mathematical Approach to RTL Verification. | David M. Russinoff |
| 2000 | FMCAD | A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon | David M. Russinoff |