Dawei Ye
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
2013–2020
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | ISCAS | A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. | Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi |
| 2019 | ISCAS | A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. | Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi |
| 2019 | ISCAS | A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. | Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi |
| 2013 | ISCAS | A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. | Dawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee |