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Debapriya Chatterjee

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

4

Active years

2009–2014

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2014DATEArChiVED: Architectural checking via event digests for high performance validation.Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco
2013DATEOn the use of GP-GPUs for accelerating compute-intensive EDA applications.Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel
2013ICCADHybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco
2012DACChecking architectural outputs instruction-by-instruction on acceleration platforms.Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco
2012DACSAGA: SystemC acceleration on GPU architectures.Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi
2012DATEApproximating checkers for simulation acceleration.Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco
2011ICCADSimulation-based signal selection for state restoration in silicon debug.Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco
2010ICCDEQUIPE: Parallel equivalence checking with GP-GPUs.Debapriya Chatterjee, Valeria Bertacco
2009DACEvent-driven gate-level simulation with GP-GPUs.Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
2009DATEGCS: High-performance gate-level simulation with GPGPUs.Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco