Dian-Lun Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
5
Active years
2021–2025
Best venue rank
A*
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | PathGen: An Efficient Parallel Critical Path Generation Algorithm. | Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang |
| 2025 | ASPDAC | HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner. | Wan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, Tsung-Wei Huang |
| 2025 | ASPDAC | iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis. | Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang |
| 2025 | DAC | iG-kway: Incremental k-way Graph Partitioning on GPU. | Wan-Luan Lee, Shui Jiang, Dian-Lun Lin, Che Chang, Boyang Zhang, Yi-Hua Chung, Ulf Schlichtmann, Tsung-Yi Ho, Tsung-Wei Huang |
| 2024 | DAC | Ink: Efficient Incremental k-Critical Path Generation. | Che Chang, Tsung-Wei Huang, Dian-Lun Lin, Guannan Guo, Shiju Lin |
| 2024 | DAC | G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner. | Wan-Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu |
| 2024 | DAC | G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis. | Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan-Luan Lee, Chih-Chun Chang, Donghao Fang, Tsung-Wei Huang |
| 2024 | EuroPar | TaroRTL: Accelerating RTL Simulation Using Coroutine-Based Heterogeneous Task Graph Scheduling. | Dian-Lun Lin, mit Y. Ogras, Joshua San Miguel, Tsung-Wei Huang |
| 2023 | DAC | GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs. | Dian-Lun Lin, Yanqing Zhang, Haoxing Ren, Brucek Khailany, Shih-Hsin Wang, Tsung-Wei Huang |
| 2023 | ICCAD | Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms. | Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang |
| 2022 | ICPP | From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus. | Dian-Lun Lin, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang |
| 2021 | EuroPar | An Experimental Study of SYCL Task Graph Parallelism for Large-Scale Machine Learning Workloads. | Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang |
| 2021 | EuroPar | Efficient GPU Computation Using Task Graph Parallelism. | Dian-Lun Lin, Tsung-Wei Huang |