| 2026 | DATE | EDA Flow Matters: Stage-Aware Parameter Optimization of Tool Chain. | Xinheng Li, Donger Luo, Peng Xu, Ziyang Yu, Qi Sun, Tinghuan Chen, Bei Yu, Hao Geng |
| 2026 | DATE | RATuner: Retrieval-Augmented VLSI Flow Design Parameter Tuning Framework. | Peng Xu, Ziyang Yu, Yuan Pu, Xinyun Zhang, Donger Luo, Hao Geng, Siyuan Xu, Tsung-Yi Ho, Bei Yu |
| 2025 | DAC | From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees. | Donger Luo, Qi Sun, Xingheng Li, Cheng Zhuo, Bei Yu, Hao Geng |
| 2025 | ICCAD | LLM-Augmented Multi-Modal Fusion for SoC Design Space Exploration. | Donger Luo, Tianyi Li, Xinheng Li, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, Hao Geng |
| 2024 | DAC | Knowing The Spec to Explore The Design via Transformed Bayesian Optimization. | Donger Luo, Qi Sun, Xinheng Li, Chen Bai, Bei Yu, Hao Geng |
| 2024 | DATE | Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics. | Donger Luo, Qi Sun, Qi Xu, Tinghuan Chen, Hao Geng |
| 2024 | ICCAD | Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture Design Optimization? | Yuanhang Gao, Donger Luo, Chen Bai, Bei Yu, Hao Geng, Qi Sun, Cheng Zhuo |