| 2025 | ASPDAC | SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. | Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma |
| 2025 | ASPDAC | A Holistic FPGA Architecture Exploration Framework for Deep Learning Acceleration. | Jiadong Zhu, Dongsheng Zuo, Yuzhe Ma |
| 2025 | ICLR | Computing Circuits Optimization via Model-Based Circuit Genetic Evolution. | Zhihai Wang, Jie Wang, Xilin Xia, Dongsheng Zuo, Lei Chen, Yuzhe Ma, Jianye Hao, Mingxuan Yuan, Feng Wu |
| 2024 | DAC | E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. | Chen Chen, Guangyu Hu, Dongsheng Zuo, Cunxi Yu, Yuzhe Ma, Hongce Zhang |
| 2024 | ICCAD | UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators. | Dongsheng Zuo, Jiadong Zhu, Chenglin Li, Yuzhe Ma |
| 2024 | ICML | A Hierarchical Adaptive Multi-Task Reinforcement Learning Framework for Multiplier Circuit Design. | Zhihai Wang, Jie Wang, Dongsheng Zuo, Yunjie Ji, Xilin Xia, Yuzhe Ma, Jianye Hao, Mingxuan Yuan, Yongdong Zhang, Feng Wu |
| 2023 | DAC | RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning. | Dongsheng Zuo, Yikang Ouyang, Yuzhe Ma |