| 2026 | ISLPED | MVP: A Mobile 3D-Stacked VLM Accelerator for Efficient Video Understanding by Leveraging Dynamic Sparse Attention Patterns. | Yifan Ding, Qianxu Wang, Dunshan Yu, Tianyu Jia |
| 2025 | CVPR | Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients. | Li Lun, Kunyu Feng, Qinglong Ni, Ling Liang, Yuan Wang, Ying Li, Dunshan Yu, Xiaoxin Cui |
| 2025 | ISCAS | A Compact Full Pipeline Architecture of SM3 Algorithm with High throughput and High Efficiency. | Tuo Li, Chao Cheng, Changhong Wang, Ruiting Wang, Xiaofeng Zou, Dunshan Yu |
| 2024 | ISCAS | An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. | Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen, Yuan Wang, Dunshan Yu, Xiaoxin Cui |
| 2022 | ISCAS | An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. | Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang |
| 2021 | ISCAS | A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. | Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang |
| 2020 | IJCNN | A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals. | Yuxuan Zhao, Jin Yang, Jinlong Lin, Dunshan Yu, Xixin Cao |
| 2018 | ASPDAC | Polymorphic gate based IC watermarking techniques. | Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui |
| 2018 | ISCAS | A 108fs | Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu |
| 2014 | ISCAS | High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2 | Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Xiao Zhang, Ying Huang, Dunshan Yu |
| 2013 | ISCAS | A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs. | Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu |
| 2006 | MMSP | An Efficient VLSI Implementation of Distributed Architecture for DWT. | Xixin Cao, Qingqing Xie, Chungan Peng, Qingchun Wang, Dunshan Yu |