| 2006 | ICCD | Iterative-Constructive Standard Cell Placer for High Speed and Low Power. | Sungjae Kim, Eugene Shragowitz |
| 2003 | ASPDAC | Transaction-based waveform analysis for IP selection. | Jian Liu, Eugene Shragowitz |
| 1995 | ASPDAC | Generic fuzzy logic CAD development tool. | Eric Q. Kang, Eugene Shragowitz |
| 1995 | ASPDAC | Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques. | Jung-Yong Lee, Eugene Shragowitz |
| 1995 | ISCAS | Performance Driven Technology Mapper for FPGAs with Complex Logic Block Structures. | Jun-Yong Lee, Eugene Shragowitz |
| 1993 | ICCAD | Bounds on net lengths for high-speed PCB. | Jaebum Lee, Eugene Shragowitz, David J. Poli |
| 1992 | DAC | Fuzzy Logic Approach to Placement Problem. | Rung-Bin Lin, Eugene Shragowitz |
| 1991 | DAC | Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. | Suphachai Sutanthavibul, Eugene Shragowitz |
| 1990 | DAC | An Adaptive Timing-Driven Layout for High Speed VLSI. | Suphachai Sutanthavibul, Eugene Shragowitz |
| 1990 | DAC | An Analytical Approach to Floorplan Design and Optimization. | Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen |
| 1990 | ICCAD | Timing Constraints for Correct Performance. | Habib Youssef, Eugene Shragowitz |
| 1989 | ICCAD | Critical path issue in VLSI design. | Habib Youssef, Eugene Shragowitz, Lionel Bening |
| 1987 | ICPP | A Hypecube Algorithm for the 0/1 Knapsack Problem. | Jong Lee, Sartaj Sahni, Eugene Shragowitz |
| 1986 | DAC | Automated layout synthesis in the YASC silicon compiler. | David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin |
| 1986 | DAC | Simulated annealing and combinatorial optimization. | Surendra Nahar, Sartaj Sahni, Eugene Shragowitz |
| 1985 | DAC | Experiments with simulated annealing. | Surendra Nahar, Sartaj Sahni, Eugene Shragowitz |