Gennady Feygin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
1991–2015
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | WCNC | Relaxed channel polarization for reduced complexity polar coding. | Mostafa El-Khamy, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang |
| 1996 | FCCM | RACER: a reconfigurable constraint-length 14 Viterbi decoder. | David Yeh, Gennady Feygin, Paul Chow |
| 1994 | DCC | Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. | Gennady Feygin, P. Glenn Gulak, Paul Chow |
| 1993 | DCC | Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. | Gennady Feygin, P. Glenn Gulak, Paul Chow |
| 1993 | ISCAS | A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. | Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton |
| 1991 | ICASSP | Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. | Gennady Feygin, Patrick Glenn Gulak, Paul Chow |