Ghassan Chehaibar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
1996–2025
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DATE | c2c-gem5: Full System Simulation of Cache-Coherent Chip-to-Chip Interconnects. | Luis Bertran Alvarez, Ghassan Chehaibar, Stephen Busch, Pascal Benoit, David Novo |
| 2009 | AINA | Modeling Multiprocessor Cache Protocol Impact on MPI Performance. | Ghassan Chehaibar, Meriem Zidouni, Radu Mateescu |
| 2004 | FORTE | Integrating Formal Verification with Mur ? of Distributed Cache Coherence Protocols in FAME Multiprocessor System Design. | Ghassan Chehaibar |
| 1996 | FORTE | Specification and Verification of the PowerScale | Ghassan Chehaibar, Hubert Garavel, Laurent Mounier, Nadia Tawbi, Ferruccio Zulian |