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Hae-Seung Lee

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

3

Active years

2003–2025

Best venue rank

A*

Where they publish

Papers

9 indexed papers, newest first.

Year	Venue	Title	Authors
2025	ISCAS	Mitigation of Vertical Fixed Pattern Noise in CMOS Image Sensors through Analog Offset Dithering and Dynamic Clock Adjustment.	Jaejin Jung, Sungyong Kim, Shinhwan Lim, Kyoungmin Koh, Hae-Seung Lee
2022	ISLPED	A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications.	Ruicong Chen, H. T. Kung, Anantha P. Chandrakasan, Hae-Seung Lee
2020	DAC	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning.	Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2018	ISCAS	Recode then LSB-first SAR ADC for Reducing Energy and Bit-cycles.	Harneet Singh Khurana, Anantha P. Chandrakasan, Hae-Seung Lee
2018	ISCAS	Design of a 6	Xi Yang, Hae-Seung Lee
2016	ISCAS	Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators.	Xi Yang, Hae-Seung Lee
2010	ISCAS	Offset cancellation for zero crossing based circuits.	Albert Chow, Hae-Seung Lee
2007	ISCAS	Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits.	Albert Chow, Hae-Seung Lee
2003	ISCAS	Output impedance requirements for DACs.	Susan Luschas, Hae-Seung Lee